1. Field of the Invention
This invention relates to logic circuits, and more particularly, to techniques for improving performance of match line circuits.
2. Description of the Related Art
In some digital logic applications, a need may arise to combine a substantial number of logic signals into one or more other signals according to a particular logic function. For example, whether two N-bit binary data patterns of match one another may be a function of whether each bit of one pattern matches a respective bit of the other pattern, for each bit within the patterns. Specifically, the overall matching condition for both patterns may be a logical AND of the matching condition for each bit position within the patterns.
However, as N increases, so does the complexity of quickly and efficiently combining a large number of signals into a particular matching function, such as an AND function. For example, using logic gates employing static CMOS (complementary metal-oxide semiconductor) circuit styles, in many process technologies logic gate size and performance degrades quickly for gates having more than three or four inputs. Consequently, multiple levels of static logic gates may need to be hierarchically employed to implement wide combinatorial functions, increasing implementation area and evaluation latency.
Conventional dynamic circuit styles may improve evaluation speed of wide functions relative to static circuit styles. For example, a conventional dynamic implementation of a wide OR-type function may include far fewer series-connected (and therefore performance-limiting) devices than its static equivalent. However, conventional dynamic circuits present challenges with respect to power consumption, noise sensitivity, and synchronization with other circuits, for example.